NSMBW-Decomp
A decompilation of New Super Mario Bros. Wii
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vihardware.h
1#ifndef RVL_SDK_VI_HARDWARE_H
2#define RVL_SDK_VI_HARDWARE_H
3#include <types.h>
4#ifdef __cplusplus
5extern "C" {
6#endif
7
8/**
9 * VI hardware registers
10 */
11volatile u16 VI_HW_REGS[64] AT_ADDRESS(0xCC002000);
12
13/**
14 * Hardware register indexes
15 */
16typedef enum {
17 VI_VTR, //!< 0xCC002000
18 VI_DCR, //!< 0xCC002002
19 VI_HTR0_H, //!< 0xCC002004
20 VI_HTR0_L, //!< 0xCC002006
21 VI_HTR1_H, //!< 0xCC002008
22 VI_HTR1_L, //!< 0xCC00200A
23 VI_VTO_H, //!< 0xCC00200C
24 VI_VTO_L, //!< 0xCC00200E
25 VI_VTE_H, //!< 0xCC002010
26 VI_VTE_L, //!< 0xCC002012
27 VI_BBEI_H, //!< 0xCC002014
28 VI_BBEI_L, //!< 0xCC002016
29 VI_BBOI_H, //!< 0xCC002018
30 VI_BBOI_L, //!< 0xCC00201A
31 VI_TFBL_H, //!< 0xCC00201C
32 VI_TFBL_L, //!< 0xCC00201E
33 VI_TFBR_H, //!< 0xCC002020
34 VI_TFBR_L, //!< 0xCC002022
35 VI_BFBL_H, //!< 0xCC002024
36 VI_BFBL_L, //!< 0xCC002026
37 VI_BFBR_H, //!< 0xCC002028
38 VI_BFBR_L, //!< 0xCC00202A
39 VI_DPV, //!< 0xCC00202C
40 VI_DPH, //!< 0xCC00202E
41 VI_DI0_H, //!< 0xCC002030
42 VI_DI0_L, //!< 0xCC002032
43 VI_DI1_H, //!< 0xCC002034
44 VI_DI1_L, //!< 0xCC002036
45 VI_DI2_H, //!< 0xCC002038
46 VI_DI2_L, //!< 0xCC00203A
47 VI_DI3_H, //!< 0xCC00203C
48 VI_DI3_L, //!< 0xCC00203E
49 VI_DL0_H, //!< 0xCC002040
50 VI_DL0_L, //!< 0xCC002042
51 VI_DL1_H, //!< 0xCC002044
52 VI_DL1_L, //!< 0xCC002046
53 VI_HSW, //!< 0xCC002048
54 VI_HSR, //!< 0xCC00204A
55 VI_FCT0_H, //!< 0xCC00204C
56 VI_FCT0_L, //!< 0xCC00204E
57 VI_FCT1_H, //!< 0xCC002050
58 VI_FCT1_L, //!< 0xCC002052
59 VI_FCT2_H, //!< 0xCC002054
60 VI_FCT2_L, //!< 0xCC002056
61 VI_FCT3_H, //!< 0xCC002058
62 VI_FCT3_L, //!< 0xCC00205A
63 VI_FCT4_H, //!< 0xCC00205C
64 VI_FCT4_L, //!< 0xCC00205E
65 VI_FCT5_H, //!< 0xCC002060
66 VI_FCT5_L, //!< 0xCC002062
67 VI_FCT6_H, //!< 0xCC002064
68 VI_FCT6_L, //!< 0xCC002066
69 VI_0x68, //!< 0xCC002068
70 VI_0x6A, //!< 0xCC00206A
71 VI_VICLK, //!< 0xCC00206C
72 VI_VISEL, //!< 0xCC00206E
73 VI_0x70, //!< 0xCC002070
74 VI_HBE, //!< 0xCC002072
75 VI_HBS, //!< 0xCC002074
76 VI_0x76, //!< 0xCC002076
77 VI_0x78, //!< 0xCC002078
78 VI_0x7A, //!< 0xCC00207A
79 VI_0x7C, //!< 0xCC00207C
80} VIHwReg;
81
82// DCR - Display Configuration Register
83#define VI_DCR_ENB (1 << 0)
84#define VI_DCR_RST (1 << 1)
85#define VI_DCR_NIN (1 << 2)
86#define VI_DCR_FMT (0b11 << 8)
87
88// DI{n} - Display Interrupt Register N
89#define VI_DI_INT (1 << 15)
90#define VI_DI_ENB (1 << 12)
91
92// VICLK - VI Clock Select Register
93#define VI_VICLK_SPEED (1 << 0)
94typedef enum { VI_VICLK_27MHZ, VI_VICLK_54MHZ } VIClkSpeed;
95
96// VISEL - VI DTV Status Register
97#define VI_VISEL_COMPONENT (1 << 0)
98
99// HBE - Border HBE
100#define VI_HBE_BRDR_EN (1 << 15)
101
102#ifdef __cplusplus
103}
104#endif
105#endif